MULTIPLICATION DES MATRICES PAR UNE METHODE OPTIQUENEZHEVENKO ES; TVERDOKHLEB PE.1972; AVTOMETRIJA; S.S.S.R.; DA. 1972; NO 6; PP. 24-29; BIBL. 2 REF.Serial Issue

A VERSATILE MULTIPLYING DIGITAL-TO-ANALOG CONVERTERTHEDCHANA MOORTHY N; PLANT JB.1972; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1972; VOL. 21; NO 10; PP. 1113-1116; BIBL. 2 REF.Serial Issue

ITERATIVE SCHEMES FOR HIGH SPEED DIVISIONAHMAD M.1972; COMPUTER J.; G.B.; DA. 1972; VOL. 15; NO 4; PP. 333-336; BIBL. 10 REF.Serial Issue

SUR UNE METHODE DE MULTIPLICATION ET DE DIVISION DES NOMBRES DANS LES DISPOSITIFS DE TRAITEMENT DES DONNEESBAGDAT'EV LT; GINZBURG M YA.1972; AVTOMETRIJA; S.S.S.R.; DA. 1972; NO 2; PP. 47-50; BIBL. 4 REF.Serial Issue

A FLEXIBLE RATE MULTIPLIER CIRCUIT WITH UNIFORM PULSE DISTRIBUTION OUTPUTSOBERMAN RMM.1972; I.E.E.E. TRANS. COMPUTERS.; U.S.A.; DA. 1972; VOL. 21; NO 8; PP. 896-899; BIBL. 3 REF.Serial Issue

MULTIPLE OPERAND ADDITION AND MULTIPLICATIONSHANKER SINGH; WAXMAN R.1973; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1973; VOL. 22; NO 2; PP. 113-120; BIBL. 4 REF.Serial Issue

HIGH-SPEED MULTIPLICATION SYSTEMSKAMAL AA; GHANNAM MAN.1972; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1972; VOL. 21; NO 9; PP. 1017-1021; BIBL. 7 REF.Serial Issue

DIFFERENTIATION DES SIGNAUX IMPULSIONNELS MODULES EN FREQUENCE ET DEFORMES PAR DES BRUITSPALAMARYUK GO; NIKIFOROV MB.1973; AVTOMAT. VYCHISLIT. TEKH., LATV. S.S.R.; S.S.S.R.; DA. 1973; NO 2; PP. 92-95; BIBL. 2 REF.Serial Issue

Analyse et commande des systèmes linéaires à coefficients périodiques = Analysis and control of linear periodic systemsRabenasolo, Andriamaherison Besoa; Richard, Jean-Pierre.1992, 207 p.Thesis

A NEW LINE OF HIGH-ACCURACY COMPUTING ELEMENTS BASED ON MODERN SEMICONDUCTOR TECHNOLOGYGILOI WK; WALDSCHMIDT K.1972; SIMULATION; U.S.A.; DA. 1972; VOL. 19; NO 2; PP. 61-69; BIBL. 6 REF.Serial Issue

MULTIFUNCTION THRESHOLD GATESHAMPEL D.1973; I.E.E.E. TRANSP. COMPUTERS; U.S.A.; DA. 1973; VOL. 22; NO 2; PP. 197-203; BIBL. 7 REF.Serial Issue

ALLOWABLE REGIONS FOR STABILITY MULTIPLIER CHARACTERISTICSSUNDARESHAN MK; THATHACHAR MAL.1972; A.I.A.A. J., NEW YORK; U.S.A.; DA. 1972; VOL. 10; NO 9; PP. 1246-1248; BIBL. 7 REF.Serial Issue

Contribution à l'étude des architectures systoliques pour les codes correcteurs d'erreurs = Contribution to the study of systolic architectures for error correcting codesDiab, Menouer; Poli, Alain.1992, 172 p.Thesis

ON THE CONNECTION BETWEEN MULTIPLIER WORD LENGTH LIMITATION AND ROUNDOFF NOISE IN DIGITAL FILTERSFETTWEIS A.1972; I.E.E.E. TRANS. CIRCUIT THEORY; U.S.A.; DA. 1972; VOL. 19; NO 5; PP. 486-491; BIBL. 23 REF.Serial Issue

A PRECISION CURRENT MULTIPLIER/DIVIDERBREDENKAMP GL.1972; PROC. I.E.E.E.; U.S.A.; DA. 1972; VOL. 60; NO 11; PP. 1440-1441; BIBL. 3 REF.Serial Issue

A bipolar 18K-gate variable size cell mastersliceNISHIMURA, T; SATO, H; TATSUKI, M et al.IEEE journal of solid-state circuits. 1986, Vol 21, Num 5, pp 727-732, issn 0018-9200Article

A 6K GaAs gate array with fully functional LSI personalizationPECZALSKI, A; LEE, G; KARWOSKI, S. M et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 2, pp 581-590, issn 0018-9200Article

GF(2^m) multiplication over triangular basis for design of Reed-Solomon codesFURNESS, R; BENAISSA, M; FENN, S. T. J et al.IEE proceedings. Computers and digital techniques. 1998, Vol 145, Num 6, pp 437-443, issn 1350-2387Article

VLSI design for diminished-1 multiplication of integers modulo a Fermat numberBENAISSA, M; PAJAYAKRIT, A; DLAY, S. S et al.IEE proceedings. Part E. Computers and digital techniques. 1988, Vol 135, Num 3, pp 161-164, issn 0143-7062Article

SPIM: a pipelined 64×64-bit iterative multiplierSANTORO, M. R; HOROWITZ, M. A.IEEE journal of solid-state circuits. 1989, Vol 24, Num 2, pp 487-493, issn 0018-9200Article

Low-temperature CMOS 8×8 bit multipliers with sub-10-ns speedsHANAMURA, S; AOKI, M; MASUHARA, T et al.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 1, pp 94-100, issn 0018-9383Article

BIT-MAP CAD and electron-beam direct lithography for bottom-up IC designSHONO, K; RYO-IL KANG.Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E. 1987, Vol 70, Num 7, pp 641-645, issn 0387-236XArticle

Balanced delay trees and combinatorial division in VLSIZURAS, D; MCALLISTER, W. H.IEEE journal of solid-state circuits. 1986, Vol 21, Num 5, pp 814-819, issn 0018-9200Article

Testing of a NORA CMOS serial-parallel multiplierBAYOUMI, M. A; NAM LING.IEEE journal of solid-state circuits. 1989, Vol 24, Num 2, pp 494-503, issn 0018-9200Article

Superchip architecture for implementing large integrated systemsCHEN, W; MAVOR, J; DENYER, P. B et al.IEE proceedings. Part E. Computers and digital techniques. 1988, Vol 135, Num 3, pp 137-150, issn 0143-7062Article